New HDL Research Challenges posed by Dynamically

Dynamically re-programmable hardware (e.g. Field Programmable Gate Arrays or FPGAs) change many of our basic assumptions of what hardware is. Normal hardware design focuses on the development of a static circuit of xed size, topology and functionality. The static nature of the target design entity is re ected in the design of CAD tools, hardware description languages, net-list representations and design methodologies. In this paper, the new research challenges for hardware description languages posed by dynamically reprogrammable hardware are identi ed. In particular, the need to specify topological information in concert with behaviour speci cation for e ective realisation of limited resources is stressed. It is shown how an existing hardware description language, Ruby, can address some of these issues. Powerful parameterised recursive descriptions of butter y networks are used to demonstrate how di erent realisations can be derived from a single speci cation. This allows di erent con gurations on FPGAs to be described in a systematic and high level manner.